IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Title Publication Date Language Citations
Optimizing power using transformations1995/01/01101
Symbolic model checking for sequential circuit verification1994/04/0199
A new discretization strategy of the semiconductor equations comprising momentum and energy balance1988/01/0199
Theory of latency-insensitive design2001/01/0195
Broad-side delay test1994/01/0188
An analytical delay model for RLC interconnects1997/01/0186
Transition density: a new measure of activity in digital circuits1993/01/0184
Prediction of analog performance parameters using fast transient testing2002/03/0182
A new algorithm for elimination of common subexpressions1999/01/0182
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates1994/01/0181
Techniques for minimizing power dissipation in scan and combinational circuits during test application1998/01/0180
NOVA: state assignment of finite state machines for optimal two-level logic implementation1990/01/0180
Equivalent Elmore delay for RLC trees2000/01/0178
Numerical methods for the hydrodynamic device model: subsonic flow1989/05/0178
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search2000/06/0177
MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems1998/01/0176
Circuit analysis and optimization driven by worst-case distances1994/01/0176
MUSTANG: state assignment of finite state machines targeting multilevel logic implementations1988/12/0174
Path-based scheduling for synthesis1991/01/0174
BLADES: an artificial intelligence approach to analog circuit design1989/06/0173
Crosstalk reduction for VLSI1997/03/0172
Artificial parameter homotopy methods for the DC operating point problem1993/06/0171
Ratio cut partitioning for hierarchical designs1991/07/0171
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization1993/01/0171
The analysis of one-dimensional linear cellular automata and their aliasing properties1990/07/0169
Selection of lumped element models for coupled lossy transmission lines1992/07/0169
Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique1992/03/0167
Detection of catastrophic faults in analog integrated circuits1989/01/0166
Berkeley reliability tools-BERT1993/01/0165
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits1995/01/0164