IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Title Publication Date Language Citations
Hierarchical finite state machines with multiple concurrency models1999/06/0163
Algorithms for hardware allocation in data path synthesis1989/07/0163
Power optimization of variable-voltage core-based systems1999/01/0163
Unified complete MOSFET model for analysis of digital and analog circuits1996/01/0163
Cell-level placement for improving substrate thermal distribution2000/01/0163
Constraint-based watermarking techniques for design IP protection2001/01/0162
Multi-level logic minimization using implicit don't cares1988/06/0161
Combinational test generation using satisfiability1996/01/0158
Solution of the hydrodynamic device model using high-order nonoscillatory shock capturing algorithms1991/01/0158
Distributed genetic algorithms for the floorplan design problem1991/04/0157
Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits1998/04/0156
RICE: rapid interconnect circuit evaluation using AWE1994/06/0155
A genetic approach to standard cell placement using meta-genetic parameter optimization1990/05/0155
Hierarchical analysis of power distribution networks2002/01/0155
Models and algorithms for bounds on leakage in CMOS circuits1999/06/0155
Nonlinear transformer model for circuit simulation1991/04/0154
Event-driven power management2001/07/0154
Full-wave PEEC time-domain method for the modeling of on-chip interconnects2001/07/0154
High-level power modeling, estimation, and optimization1998/01/0154
An exact zero-skew clock routing algorithm1993/01/0153
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation1999/07/0153
Faster maximum and minimum mean cycle algorithms for system-performance analysis1998/01/0153
Integrated circuit design optimization using a sequential strategy1992/03/0153
Hierarchical approach to "atomistic" 3-D MOSFET simulation1999/01/0151
Scan-based transition test1993/01/0151
Optimal wiresizing under Elmore delay model1995/03/0150
Application of statistical design and response surface methods to computer-aided VLSI device design1988/01/0150
COMPACTEST: a method to generate compact test sets for combinational circuits1993/07/0150
A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs1989/04/0150
A CMOS fault extractor for inductive fault analysis1988/01/0150