Double Node Upsets Hardened Latch Circuits

Article Properties
Cite
Li, Yuanqing, et al. “Double Node Upsets Hardened Latch Circuits”. Journal of Electronic Testing, vol. 31, no. 5-6, 2015, pp. 537-48, https://doi.org/10.1007/s10836-015-5551-3.
Li, Y., Wang, H., Yao, S., Yan, X., Gao, Z., & Xu, J. (2015). Double Node Upsets Hardened Latch Circuits. Journal of Electronic Testing, 31(5-6), 537-548. https://doi.org/10.1007/s10836-015-5551-3
Li Y, Wang H, Yao S, Yan X, Gao Z, Xu J. Double Node Upsets Hardened Latch Circuits. Journal of Electronic Testing. 2015;31(5-6):537-48.
Journal Categories
Technology
Electrical engineering
Electronics
Nuclear engineering
Electric apparatus and materials
Electric circuits
Electric networks
Technology
Electrical engineering
Electronics
Nuclear engineering
Electronics
Refrences
Refrences Analysis
The category Technology: Electrical engineering. Electronics. Nuclear engineering: Electric apparatus and materials. Electric circuits. Electric networks 21 is the most frequently represented among the references in this article. It primarily includes studies from IEEE Transactions on Nuclear Science The chart below illustrates the number of referenced publications per year.
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Citations
Citations Analysis
The first research to cite this article was titled A 65 nm Temporally Hardened Flip-Flop Circuit and was published in 2016. The most recent citation comes from a 2024 study titled A 65 nm Temporally Hardened Flip-Flop Circuit . This article reached its peak citation in 2020 , with 10 citations.It has been cited in 18 different journals, 5% of which are open access. Among related journals, the IEEE Transactions on Aerospace and Electronic Systems cited this research the most, with 6 citations. The chart below illustrates the annual citation trends for this article.
Citations used this article by year