Is low power design the key to future electronics? This paper presents a comprehensive survey of Computer-Aided Design (CAD) methodologies and techniques aimed at minimizing power consumption in digital CMOS circuits and systems. This article addresses challenges and solutions across architectural, logical, and physical levels of abstraction, offering a valuable resource for designers seeking to optimize energy efficiency. The paper explores various techniques, such as dynamic voltage and frequency scaling, clock gating, and power-aware logic synthesis, to reduce power dissipation. It delves into the intricacies of architectural-level optimizations, including algorithm selection and hardware partitioning, as well as logic-level techniques like transistor sizing and technology mapping. Furthermore, the survey discusses physical-level considerations such as layout optimization and interconnect design. This review emphasizes the significance of power minimization in modern electronic design. As technology scales down, power dissipation becomes a critical factor limiting performance and reliability. Addressing these challenges is essential for developing high-performance, energy-efficient systems, particularly in portable devices and embedded applications.
Published in ACM Transactions on Design Automation of Electronic Systems, this survey aligns with the journal's focus on methodologies and tools for electronic system design. By providing a comprehensive overview of power minimization techniques, this article contributes significantly to the journal's goal of advancing research in design automation and low-power electronic systems.