IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Title	Publication Date	Citations
Worst-case analysis and optimization of VLSI circuit performances	1995/04/01	37
Efficient reconfiguration algorithms for degradable VLSI/WSI arrays	1992/01/01	37
Global routing by new approximation algorithms for multicommodity flow	2001/05/01	37
Fingerprinting techniques for field-programmable gate array intellectual property protection	2001/01/01	37
Global routing based on Steiner min-max trees	1990/01/01	37
A method of fault analysis for test generation and fault diagnosis	1988/07/01	37
A realistic fault model and test algorithms for static random access memories	1990/06/01	37
Using statecharts for hardware description and synthesis	1989/07/01	36
An efficient algorithm for finding multiple DC solutions based on the SPICE-oriented Newton homotopy method	2002/03/01	36
A transitive closure algorithm for test generation	1993/07/01	36
Automatic synthesis of low-power gated-clock finite-state machines	1996/06/01	36
A fast hierarchical algorithm for three-dimensional capacitance extraction	2002/03/01	35
Continuous signature monitoring: low-cost concurrent detection of processor control errors	1990/06/01	35
Exact algorithms for output encoding, state assignment, and four-level Boolean minimization	1991/01/01	35
Fast evaluation of sequence pair in block placement by longest common subsequence computation	2001/01/01	34
An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations	1990/03/01	34
An efficient methodology for building macromodels of IC fabrication processes	1989/01/01	34
A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language	2001/01/01	34
Pipeline vectorization	2001/01/01	34
Stochastic modeling of a power-managed system-construction and optimization	2001/01/01	34
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement	1990/03/01	34
Algorithms and models for cellular based topography simulation	1995/01/01	34
Architectural synthesis for DSP silicon compilers	1989/04/01	34
Parametric yield optimization for MOS circuit blocks	1988/06/01	33
AMGIE-A synthesis environment for CMOS analog integrated circuits	2001/01/01	33
Integer programming based topology selection of cell-level analog circuits	1995/04/01	33
A globally and quadratically convergent algorithm for solving nonlinear resistive networks	1990/05/01	33
Synthesis of robust delay-fault-testable circuits: theory	1992/01/01	33
Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits	2002/05/01	33
Analysis of cyclic combinational circuits	1994/07/01	33

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