IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Titel Veröffentlichungsdatum Sprache Zitate
A directed search method for test generation using a concurrent simulator1989/01/0126
Bit-fixing in pseudorandom sequences for scan BIST2001/04/0126
Architectures and synthesis algorithms for power-efficient bus interfaces2000/01/0126
Analysis and future trend of short-circuit power2000/01/0126
Floorplanning using a tree representation2001/01/0126
MUSE: a multilevel symbolic encoding algorithm for state assignment1991/01/0125
Measurements and analyses of substrate noise waveform in mixed-signal IC environment2000/06/0125
A modeling technique for CMOS gates1999/05/0125
Closing the gap: near-optimal Steiner trees in polynomial time1994/01/0125
Time-domain simulation of multiconductor transmission lines with frequency-dependent losses1992/01/0125
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction1992/01/0125
Automated synthesis of phase shifters for built-in self-test applications2000/01/0125
Combinational and sequential logic optimization by redundancy addition and removal1995/07/0125
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences1993/01/0125
Architectural partitioning for system level synthesis of integrated circuits1991/07/0125
Creating small fault dictionaries [logic circuit fault diagnosis]1999/03/0125
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design1995/07/0125
The efficient simulation of coupled point defect and impurity diffusion1988/01/0125
Efficient and effective placement for very large circuits1995/03/0125
An Esterel compiler for large control-dominated systems2002/01/0125
An analytical approach to floorplan design and optimization1991/06/0124
Optimal partitioners and end-case placers for standard-cell layout2000/01/0124
Time-domain macromodels for VLSI interconnect analysis1994/01/0124
Minimal buffer insertion in clock trees with skew and slew rate constraints1997/04/0124
Numerical simulation of the gas immersion laser doping (GILD) process in silicon1988/01/0124
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters2002/01/0124
Retiming and resynthesis: optimizing sequential networks with combinational techniques1991/01/0124
Three-dimensional capacitance computations for VLSI/ULSI interconnections1989/01/0124
BEAVER: a computational-geometry-based tool for switchbox routing1988/06/0124
A parity bit signature for exhaustive testing1988/03/0124