IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Titel	Veröffentlichungsdatum	Zitate
Estimating routing congestion using probabilistic analysis	2002/01/01	33
On the reconfiguration of degradable VLSI/WSI arrays	1997/01/01	33
Hierarchical test generation using precomputed tests for modules	1990/06/01	33
ESp: Placement by simulated evolution	1989/03/01	33
Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques	1997/05/01	32
A small-signal MOSFET model for radio frequency IC applications	1997/05/01	32
An edge-based heuristic for Steiner routing	1994/01/01	32
Telescopic units: a new paradigm for performance optimization of VLSI designs	1998/03/01	32
Two-dimensional modeling of ion implantation induced point defects	1988/01/01	32
Inverter models of CMOS gates for supply current and delay evaluation	1994/01/01	32
Incorporating bottom-up design into hardware synthesis	1990/01/01	32
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution	1995/01/01	32
Design of mixed-signal systems-on-a-chip	2000/01/01	32
Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's	1999/05/01	32
Techniques for the creation of digital watermarks in sequential circuit designs	2001/01/01	32
Low-power scan testing and test data compression for system-on-a-chip	2002/05/01	31
High-level DSP synthesis using concurrent transformations, scheduling, and allocation	1995/03/01	31
Logic emulation with virtual wires	1997/06/01	31
Automatic generation of analytical models for interconnect capacitances	1995/04/01	31
The ellipsoidal technique for design centering and region approximation	1991/01/01	31
An integrated CAD system for algorithm-specific IC design	1991/04/01	31
Techniques for area estimation of VLSI layouts	1989/01/01	31
A detailed router for field-programmable gate arrays	1992/05/01	31
Forward-looking fault simulation for improved static compaction	2001/01/01	31
Three-dimensional resist process simulator PEACE (photo and electron beam lithography analyzing computer engineering system)	1991/06/01	31
Multilevel circuit partitioning	1998/01/01	31
Simulating and testing oversampled analog-to-digital converters	1988/06/01	31
Test generation and verification for highly sequential circuits	1991/05/01	31
Datapath synthesis using a problem-space genetic algorithm	1995/01/01	31
A computationally efficient unified approach to the numerical analysis of the sensitivity and noise of semiconductor devices	1993/03/01	31

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