IEEE Transactions on Circuits and Systems II: Express Briefs

Titel Veröffentlichungsdatum Sprache Zitate
Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications1992/01/0152
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit1993/01/0152
Area-time-power tradeoffs in parallel adders1996/01/0151
Reduced-order modeling of time-varying systems1999/01/0150
Oversampled cosine modulated filter banks with perfect reconstruction1998/01/0150
A new current-controlled multiphase sinusoidal oscillator using translinear current conveyors1998/07/0150
Design of recursive 1-D variable filters with guaranteed stability1997/01/0149
Synchronizing hyperchaotic systems by observer design1999/04/0149
Versatile insensitive current-mode universal biquad implementation using current conveyors2001/04/0149
Structural properties of gradient recurrent high-order neural networks1995/01/0149
Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays2000/07/0149
Optimal parameters for ΔΣ modulator topologies1998/01/0149
Residue-to-binary arithmetic converter for the moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1)1998/01/0148
Optimized frequency-shaping circuit topologies for LDOs1998/06/0148
Design of near perfect reconstruction oversampled filter banks for subband adaptive filters1999/01/0147
Multifunction biquadratic filters using current conveyors1997/01/0146
Design of quadrature mirror filters with linear phase in the frequency domain1992/01/0146
Design of the lower error fixed-width multiplier and its application2000/01/0145
An autozeroing floating-gate amplifier2001/01/0145
Sparsely interconnected neural networks for associative memories with applications to cellular neural networks1994/04/0145
A Remez exchange algorithm for orthonormal wavelets1994/01/0145
Multiwavelet prefilters. 1. Orthogonal prefilters preserving approximation order p≤21998/01/0144
Winner-take-all cellular neural networks1993/03/0143
A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation2000/01/0143
A low-voltage low-power wide-range CMOS variable gain amplifier1998/07/0143
A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation2000/04/0143
IIR multiple notch filter design based on allpass filter1997/01/0143
Algorithms for low power and high speed FIR filter realization using differential coefficients1997/06/0142
A coding theory approach to error control in redundant residue number systems. I. Theory and single error correction1992/01/0142
Delta-Sigma modulator based A/D conversion without oversampling1995/01/0142