SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs

Article Properties
Journal Categories
Science
Mathematics
Instruments and machines
Electronic computers
Computer science
Science
Mathematics
Instruments and machines
Electronic computers
Computer science
Computer software
Technology
Electrical engineering
Electronics
Nuclear engineering
Electric apparatus and materials
Electric circuits
Electric networks
Technology
Electrical engineering
Electronics
Nuclear engineering
Electronics
Computer engineering
Computer hardware
Refrences
Title Journal Journal Categories Citations Publication Date
A 12 nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800 MHz multi-plane NoC 2022
10.1109/IES.2006.357464
10.1145/2897937.2905018
10.1109/JPROC.2015.2480849
Theory of latency-insensitive design IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Technology: Electrical engineering. Electronics. Nuclear engineering: Electronics: Computer engineering. Computer hardware
  • Science: Mathematics: Instruments and machines: Electronic computers. Computer science
  • Technology: Electrical engineering. Electronics. Nuclear engineering: Electric apparatus and materials. Electric circuits. Electric networks
  • Technology: Electrical engineering. Electronics. Nuclear engineering: Electronics
  • Technology: Electrical engineering. Electronics. Nuclear engineering: Electronics
  • Technology: Engineering (General). Civil engineering (General)
95 2001