Title | Journal | Journal Categories | Citations | Publication Date |
---|---|---|---|---|
A 5.5 V SOPA line driver in a standard 1.2 V 0.13 μm CMOS technology | ||||
Discrete-Time Signal Processing | 2011 | |||
10.1109/LSSC.2021.3112034 | ||||
10.1109/JSSC.2018.2805872 | ||||
10.1109/JSSC.2020.3005798 |
Title | Journal | Journal Categories | Citations | Publication Date |
---|---|---|---|---|
Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology | IET Circuits, Devices & Systems |
| 1 | 2022 |