Synthesizing Hardware from Dataflow Programs
Article Properties
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LanguageEnglish
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DOI (url)
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Publication Date2009/07/11
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Indian UGC (journal)
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Refrences9
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Citations20
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Jörn W. Janneck
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Ian D. Miller
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David B. Parlour
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Ghislain Roquier
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Matthieu Wipliez
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Mickaël Raulet
Cite
Janneck, Jörn W., et al. “Synthesizing Hardware from Dataflow Programs”. Journal of Signal Processing Systems, vol. 63, no. 2, 2009, pp. 241-9, https://doi.org/10.1007/s11265-009-0397-5.
Janneck, J. W., Miller, I. D., Parlour, D. B., Roquier, G., Wipliez, M., & Raulet, M. (2009). Synthesizing Hardware from Dataflow Programs. Journal of Signal Processing Systems, 63(2), 241-249. https://doi.org/10.1007/s11265-009-0397-5
Janneck, Jörn W., Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, and Mickaël Raulet. “Synthesizing Hardware from Dataflow Programs”. Journal of Signal Processing Systems 63, no. 2 (2009): 241-49. https://doi.org/10.1007/s11265-009-0397-5.
1.
Janneck JW, Miller ID, Parlour DB, Roquier G, Wipliez M, Raulet M. Synthesizing Hardware from Dataflow Programs. Journal of Signal Processing Systems. 2009;63(2):241-9.
Journal Categories
Science
Science (General)
Cybernetics
Information theory
Technology
Electrical engineering
Electronics
Nuclear engineering
Electric apparatus and materials
Electric circuits
Electric networks
Technology
Electrical engineering
Electronics
Nuclear engineering
Electronics
Technology
Engineering (General)
Civil engineering (General)
Refrences
| Title | Journal | Journal Categories | Citations | Publication Date |
|---|---|---|---|---|
| Dataflow process networks | Proceedings of the IEEE |
| 208 | 1995 |
| 10.1109/SIPS.2007.4387565 | ||||
| 10.1109/SIPS.2008.4671776 | ||||
| 10.1109/SIPS.2007.4387595 | ||||
| 10.1109/ICASSP.2009.4959646 |
Citations
| Title | Journal | Journal Categories | Citations | Publication Date |
|---|---|---|---|---|
| Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains | IEEE Access |
| 2020 | |
| Verifying parallel dataflow transformations with model checking and its application to FPGAs | Journal of Systems Architecture |
| 3 | 2019 |
Compositional Dataflow Circuits | ACM Transactions on Embedded Computing Systems |
| 2 | 2019 |
| Modeling and Analysis of FPGA Accelerators for Real-Time Streaming Video Processing in the Healthcare Domain | Journal of Signal Processing Systems |
| 1 | 2018 |
| Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs | Computers |
| 2 | 2018 |
Citations Analysis
The category
Technology: Electrical engineering. Electronics. Nuclear engineering: Electric apparatus and materials. Electric circuits. Electric networks 13
is the most commonly referenced area in studies that cite this article. The first research to cite this article was titled Exploring the Concurrency of an MPEG RVC Decoder Based on Dataflow Program Analysis and was published in 2009. The most recent citation comes from a 2020 study titled Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains. This article reached its peak citation in 2013, with 7 citations. It has been cited in 10 different journals, 30% of which are open access. Among related journals, the Signal Processing: Image Communication cited this research the most, with 5 citations. The chart below illustrates the annual citation trends for this article.