Can FPGAs be dynamically reconfigured to optimize performance in high-demand applications? This paper explores dynamic task scheduling for FPGA-based systems, investigating how FPGAs can be utilized as computational resources in applications requiring high performance. The study addresses the challenges of resource fragmentation in systems composed of arrays of chips that can be partially reconfigured. The research examines the problem of repartitioning the system at runtime, rearranging executing tasks to allow waiting tasks to enter sooner. It introduces the problems of identifying and scheduling feasible task rearrangements, demonstrating their NP-completeness. Two heuristic approaches—Local Repacking and Ordered Compaction—are developed and compared through simulations. The results indicate potential scheduling advantages, which are jeopardized by delays to moving tasks when the average cost of reloading tasks becomes significant relative to task service periods. By introducing and evaluating heuristic approaches for task rearrangement, this research provides valuable insights into optimizing FPGA-based systems. The identification of challenges related to task movement costs offers directions for future research, with implications for high-performance computing and reconfigurable architectures.
Published in the International Journal of Foundations of Computer Science, this paper perfectly fits with the journal's scope, which focuses on theoretical foundations and practical applications in computer science. By addressing the challenges of dynamic task scheduling in FPGA-based systems, this research contributes to the journal's ongoing exploration of algorithms, computational complexity, and system optimization. The theoretical analysis combined with heuristic approaches aligns with the journal's emphasis on both theoretical rigor and practical relevance.