As quantum computing threats loom, can specialized processors offer a viable defense? This study introduces an application-specific instruction set processor (ASIP) design tailored for lattice-based cryptography (LBC) algorithms, considered promising candidates for post-quantum cryptography (PQC). Focusing on the Kyber, Saber, and NewHope algorithms, the ASIP design, based on transport triggered architecture (TTA), incorporates custom hardware accelerators for computation-intensive steps. Compared with prominent RISC-V cores and instruction set extension studies, the proposed design demonstrates superior efficiency, performance, and resource utilization in both FPGA and ASIC implementations. The research contributes a lightweight and efficient solution for implementing PQC algorithms on embedded systems, addressing the urgent need for processor designs capable of running these algorithms effectively. This offers a critical step towards securing sensitive data against future quantum attacks.
Published in the Arabian Journal for Science and Engineering, this paper aligns with the journal’s focus on engineering and technology. The design of an application-specific instruction set processor (ASIP) for post-quantum cryptography algorithms contributes to the journal’s exploration of engineering solutions for emerging technological challenges. The comparison of FPGA and ASIC implementations further fits the journal's emphasis on practical engineering applications.