IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Title Publication Date Language Citations
Circular self-test path: a low-cost BIST technique for VLSI circuits1989/01/0128
On wirelength estimations for row-based placement1999/01/0127
Compact test sets for high defect coverage1997/01/0127
SMART-P: rigorous three-dimensional process simulator on a supercomputer1988/06/0127
On computing the sizes of detected delay faults1990/03/0127
Macromodeling CMOS circuits for timing simulation1988/12/0127
Guarded evaluation: pushing power management to logic synthesis/design1998/01/0127
Principles of substrate crosstalk generation in CMOS circuits2000/06/0127
A concurrent testing technique for digital circuits1988/12/0127
Buffer insertion for noise and delay optimization1999/01/0127
Estimation of average switching activity in combinational logic circuits using symbolic simulation1997/01/0127
SAMC: a code compression algorithm for embedded processors1999/01/0127
Hybrid designs generating maximum-length sequences1988/01/0127
Temperature measurement and equilibrium dynamics of simulated annealing placements1990/03/0127
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits1994/03/0127
Preservation of passivity during RLC network reduction via split congruence transformations1998/07/0127
Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design1998/01/0127
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip2015/10/0126
Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions1992/01/0126
Estimation of maximum currents in MOS IC logic circuits1990/06/0126
Modeling digital substrate noise injection in mixed-signal IC's1999/03/0126
Irredundant sequential machines via optimal logic synthesis1990/01/0126
A compact IGFET model-ASIM1988/09/0126
Models and algorithms for three-dimensional topography simulation with SAMPLE-3D1994/01/0126
Activity-driven clock design2001/06/0126
O(n/sup 2/) algorithms for graph planarization1989/03/0126
A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]2000/07/0126
Optimal floorplan area optimization1992/01/0126
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams1996/01/0126
Clock skew verification in the presence of IR-drop in the power distribution network2000/06/0126