IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Title Publication Date Language Citations
Provably good performance-driven global routing1992/06/0149
HOPE: an efficient parallel fault simulator for synchronous sequential circuits1996/01/0149
Test set compaction algorithms for combinational circuits2000/01/0149
Automatic synthesis of asynchronous circuits from high-level specifications1989/01/0148
System-level performance analysis for designing on-chip communication architectures2001/06/0148
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning2002/01/0147
A new class of iterative Steiner tree heuristics with good performance1992/07/0147
Combined word-length optimization and high-level synthesis of digital signal processing systems2001/01/0147
Probabilistic simulation for reliability analysis of CMOS VLSI circuits1990/04/0147
Bounds and analysis of aliasing errors in linear feedback shift registers1988/01/0146
ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips1998/01/0146
Combinatorial optimization by stochastic evolution1991/04/0145
CMOS op-amp sizing using a geometric programming formulation2001/01/0145
A charge sheet capacitance model of short channel MOSFETs for SPICE1991/03/0145
Logic design verification via test generation1988/01/0145
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes1999/01/0145
Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations1997/07/0145
Minimizing production test time to detect faults in analog circuits1994/06/0144
Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations1996/05/0144
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization1994/01/0144
Canonical symbolic analysis of large analog circuits with determinant decision diagrams2000/01/0144
The Elmore delay as a bound for RC trees with generalized input signals1997/01/0144
MISNAN-a physically based continuous MOSFET model for CAD applications1991/01/0144
Testing analog and mixed-signal integrated circuits using oscillation-test method1997/07/0143
Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models1994/06/0143
Test generation for sequential circuits1988/01/0143
Module packing based on the BSG-structure and IC layout applications1998/06/0143
Crosstalk in VLSI interconnections1999/12/0143
Software-based self-testing methodology for processor cores2001/03/0143
An improved two-way partitioning algorithm with stable performance (VLSI)1991/01/0143