IEEE Transactions on Advanced Packaging

Title Publication Date Language Citations
Buried Bump and AC Coupled Interconnection Technology2004/02/01English
A Multiconductor Transmission Line Methodology for Global On-Chip Interconnect Modeling and Analysis2004/02/01English
Evolution of Organic Chip Packaging Technology forHigh Speed Applications2004/02/01English
A Novel Time-Domain Algorithm for Synthesizing Broadband Macromodels of Coupled Interconnects2004/02/01English
Development of CSP Using Au Ball Bumps as External Connection Terminals2004/02/01English
<tex>$rm Mpi rm log$</tex>, Macromodeling Via Parametric Identification of Logic Gates2004/02/01English
An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards2004/02/01
Effect of Thermal Cycling on the Adhesion Strength of<tex>$hboxSn$</tex>–<tex>$hbox9Zn$</tex>–<tex>$hboxxAg$</tex>–<tex>$hboxCu$</tex>Interface2004/02/01English
Chip-Package Co-Implementation of a Triple DES Processor2004/02/01English
Closed-Form Expressions for the Series Impedance Parameters of On-Chip Interconnects on Multilayer Silicon Substrates2004/02/01English
Accurate RF Electrical Characterization of CSPs Using MCM-D Thin Film Technology2004/02/01English
Foreword Contributions from the 11th Topical Meeting on Electrical Performance of Electronic Packaging2004/02/01English
Table of contents2004/02/01
Finite-Thickness Conductor Models for Full-Wave Analysis of Interconnects With a Fast Integral Equation Method2004/02/01English
Design of Integrated Low Noise Amplifiers (LNA) Using Embedded Passives in Organic Substrates2004/02/01English
A Performance and Manufacturability Evaluation of Bump Chip Carrier Packages2004/02/01English
A Reworkable Epoxy Resin for Isotropically Conductive Adhesive2004/02/01English
Improved Underfill Adhesion in Flip-Chip Packages by Means of Ultraviolet Light/Ozone Treatment2004/02/01English
Design, analysis, and development of novel three-dimensional stacking WLCSP2005/08/01
Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication2005/08/01
Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics2005/08/01
An analytical model for predicting the underfill flow characteristics in flip-chip encapsulation2005/08/01
Design and fabrication of a flip-chip-on-chip 3-D packaging structure with a through-silicon via for underfill dispensing2005/08/01
Real chip size three-dimensional stacked package2005/08/01
Foreword Three-Dimensional Packaging2005/08/01
Experimental wetting dynamics study of eutectic and lead-free solders with various fluxes, isothermal conditions, and bond pad metallizations2005/08/01
Environmental qualification testing and failure analysis of embedded resistors2005/08/01
Optimization for chip stack in 3-D packaging2005/08/01
Comprehensive broad-band electromagnetic modeling of on-chip interconnects with a surface discretization-based generalized PEEC model2005/08/01
Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias2005/08/01